1. Field of the Invention
The present invention relates to improvements in a method for manufacturing an epitaxial wafer used for a highly integrated semiconductor device, and, more particularly to a method for manufacturing an epitaxial wafer, which aims at forming an epitaxial layer on a silicon wafer sliced from silicon single crystal that grows based on a Czochralski process (hereinafter referred to as “CZ process”).
2. Description of the Related Art
Hitherto, an epitaxial wafer used as a substrate of a highly integrated device has been fabricated by forming an epitaxial layer on a silicon wafer sliced from a silicon single crystal that grows based on a Czochralski process (hereinafter referred to as “CZ process”).
The CZ process is a method of melting polysilicon filled in a crucible under heating with a heater and then dipping seed crystal into a surface portion of the silicon melt to rotate and allow the crystal to grow, and pulling up the crystal to complete a single crystal. If a surface of a silicon wafer (hereinafter referred to as “epi-sub wafer) sliced from the single crystal formed with the CZ process involves dislocation or crystal defects such as oxygen-induced stacking faults (hereinafter referred to as “OSFs”), an epitaxial layer formed on the epi-sub wafer surface has epitaxial defects due to these defects.
The epitaxial defects cause an increase in leak current or a decrease in lifetime in a device active region of a wafer on which fine circuit patterns are formed in response to recent tendencies to increase the device integration degree. Thus, the epitaxial defects should be reduced or removed.
However, there is a problem that even if an epitaxial wafer having high crystallinity with few epitaxial defects is used, device characteristics would be degraded in the case where an epitaxial layer is contaminated with metal impurities in a subsequent device process.
The higher the device integration degree, the more the process is complicated and the more the epitaxial layer is contaminated. As a result, the contamination of the epitaxial layer with impurities of metal elements largely affects the finished quality. Basically, a metal contaminant is prevented by performing the entire process under a clean atmosphere with clean materials. However, it is difficult to completely remove the metal contaminant in the device process. As a countermeasure against this problem, development of a gettering technique for the epi-sub wafer is important. The gettering technique is a process of getting impurity elements that intrude into the epitaxial layer due to contamination, out of the device active region toward a gettering sink, and rendering the elements harmless in the device active region.
To describe an example of the gettering technique, so-called intrinsic gettering (hereinafter referred to as “IG”) has been known. This technique traps impurity elements with a bulk micro defect (hereinafter referred to as “BMD”) induced during heat treatment of the device process. However, a silicon wafer is subjected to high-temperature heat treatment at 1050 to 1200° C. during a step of forming an epitaxial layer. As a result, minute nuclei of oxygen precipitation in a wafer sliced from silicon single crystal are reduced and annihilated, making it difficult to induce enough BMDs as a gettering source in the wafer. This causes a problem in that even if the gettering technique is applied, the IG is not so effective against the metal impurities throughout the entire process.
To that end, proposed is a manufacturing method for suppressing generation of epitaxial defects to fabricate an epitaxial wafer with a high IG effect (for example, refer to Patent Document 1). This method rapidly reduces the temperature of silicon single crystal at a cooling rate of 3.0° C./min or more (hereinafter referred to “rapid cooling”) while the silicon single crystal being passed through a temperature region of 1100 to 900° C. during a pulling step to reduce a size of each nucleus of oxygen precipitation to a micronuclei to thereby largely suppress generation of the epitaxial defects.
To detail this method, in the case where silicon single crystal having a diameter of 200 mm is allowed to grow in a crucible containing boron-doped silicon melt in a chamber based on the CZ process, the silicon single crystal is pulled up to a length of 500 mm at a pulling rate of 1.1 mm/min to form a straight body and then further pulled up to the length of 550 mm at a higher pulling rate of 1.8 mm/min. Subsequently, the pulling rate is set to 1.1 mm/min again, and the silicon single crystal is pulled to the length of 1000 mm. By changing the pulling rate in this way, the silicon single crystal can be rapidly cooled at a cooling rate of 3° C./min or more while passed through a temperature region of 1100 to 900° C. during the pulling step. A silicon wafer sliced from the silicon single crystal is subjected to heat treatment for 2 hours at 850° C. in a mixed atmosphere of oxygen and an inert gas. Owing to the heat treatment, thermal stability of the nuclei of oxygen precipitation in the crystal of the silicon wafer increases, so BMDs are neither reduced nor annihilated even through the high-temperature heat treatment in the epitaxial layer forming step. Then, the heat-treated silicon wafer is mirror-polished and then placed in an epitaxial device and subjected to hydrogen baking for 1 minute at 1150° C. Following this, a material gas is supplied while the device temperature is set and kept at 1075° C. for a predetermined period. As a result, a 5 μm-thick epitaxial layer is formed on the wafer surface to complete an epitaxial wafer.
However, in the process of pulling a silicon single crystal, a cooling rate tends to differ between a central portion and a peripheral portion of the silicon single crystal due to a structural problem that the central portion is difficult to cool but the peripheral portion is easy to cool. A single crystal having a diameter of 300 mm strongly shows this tendency. It is difficult to attain cooling conditions that the cooling rate is 3° C./min or more in the central portion. Even in the case where the cooling conditions that the cooling rate is 3° C./min or more are satisfied by placing a coolant, if the single crystal involves dislocation, cracks might develop in the single crystal due to a residual stress caused by excessive rapid cooling. In this case, there is a fear that the single crystal cannot be pulled up. Therefore, it is difficult to apply the cooling conditions disclosed in Patent Document 1 to growth of single crystal having the diameter of 300 mm or more as it is.
Patent Document 1
Japanese Unexamined Patent Application Publication No. 2004-91221 (claims 5 and 7, paragraphs [0013] to [0017], [0023], [0024], [0026], and [0027] in the specification, FIG. 1